HSIO System Firmware Engineer

상세 직무 내용

About the Job Our HSIO (High-Speed IO) team builds the interconnect backbone that lets Rebellions' AI SoCs scale up — from in-package die-to-die (UCIe) to rack-scale — and scale out across the datacenter (node-to-node). This fabric sits at the very center of next-generation AI compute. The team already brings together architecture, IP level firmware, RTL design, and PSI (Power & Signal Integrity) expertise. What we're missing is a SW/FW engineer who can drive NPU system-level control during HSIO IP testing — the person who makes the system do what an experiment needs. You'll be the bridge between vendor HSIO IP evaluation and Rebellions' own system platform. Responsibilities and Opportunities To test and evaluate vendor HSIO IP (starting with D2D/UCIe), develop, modify, and maintain the NPU system-level firmware (on our existing system-FW base) needed to drive the IP under real system conditions. Own and build the test software environment (integrating vendor-provided tools and building on-demand tooling), with reproducibility and reusability in mind so it can grow into an automation-ready regression foundation. Run a portion of HSIO IP test & evaluation and analyze the resulting data — as everyone on the team does. Support silicon bring-up & validation in collaboration with the dedicated Bring-up team (you own the NPU system control needed to exercise the IP; the Bring-up team owns chip-level post-silicon bring-up). As the HSIO roadmap expands beyond D2D/UCIe — to other interconnect IP now, and longer-term to Ethernet / Optics — you'll extend the same system-FW and validation capability to new IP. You won't ride one interconnect generation; you'll ride all of them. Key Qualifications 2–6 years of system firmware experience (embedded systems, device drivers, or system software). Exceptional fresh MS graduates with hands-on bring-up / embedded experience may also be considered. Ability and willingness to read and understand HSIO specifications at the structural / system level (register maps, link-layer protocol). Analog-level(SerDes/PHY) depth is not a requirement through it could be a bonus if you have it. Proficiency in C / C++ / Python and firmware-level debugging. Working-level English communication — you will work directly with global HSIO IP vendors. Strong cross-functional communication (architecture / design / validation). Ideal Qualifications Experience in silicon bring-up (at least one tape-out cycle from pre-silicon to post-silicon). 5+ years of system FW, or chip-level bring-up & debugging experience. HSIO analog-level understanding (SerDes/PHY, equalization, eye-diagram interpretation). Embedded debug experience: RTOS / bare-metal FW (ARM Cortex-A/M, RISC-V) and/or HW debug tools (JTAG, logic analyzer, oscilloscope). Familiarity with high-speed interconnects such as UCIe or PCIe. Note: prior HSIO / UCIe experience is NOT required. We are looking for a strong system-firmware engineer who is excited to learn high-speed interconnect at the system level — we'll point you at UCIe. 전형절차 서류전형 > On-line 인터뷰 > On-site 인터뷰 > Culture-fit 인터뷰 > 처우 협의 > 최종 합격 전형절차는 직무별로 다르게 운영될 수 있으며, 일정 및 상황에 따라 변동될 수 있습니다. 전형 일정 및 결과는 지원 시 작성하신 이메일로 개별 안내드립니다. 참고사항 본 공고는 모집 완료 시 조기 마감될 수 있습니다. 지원서 내용 중 허위사실이 있는 경우에는 합격이 취소될 수 있습니다. 채용 및 업무 수행과 관련하여 요구되는 법령 상 자격이 갖추어지지 않은 경우 채용이 제한될 수 있습니다. 보훈 대상자 및 장애인 여부는 채용 과정에서 어떠한 불이익도 미치지 않습니다. 담당 업무 범위는 후보자의 전반적인 경력과 경험 등 제반사정을 고려하여 변경될 수 있습니다. 이러한 변경이 필요할 경우, 최종 합격 통지 전 적절한 시기에 후보자와 커뮤니케이션 될 예정입니다. 채용 관련 문의사항은 아래 메일 주소로 문의바랍니다. recruit@rebellions.ai